1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly, it relates to a test mode setting circuit which can facilitate to set an operation test mode in, e.g., a large-scale integrated circuit memory device.
2. Description of the Prior Art
As high integration of semiconductor integrated circuits has advanced, a number of functions have been assembled in a single chip, followed by complication in circuitry and operation.
Such a highly integrated semiconductor integrated circuit is generally multi-functional, and hence it requires a number of input/output terminals. On the other hand, such complication of the semiconductor integrated circuit reduces its observability and controllability of internal operation etc., whereby an operation test for the semiconductor integrated circuit cannot be performed with only input/output terminals generally provided therein. In order to facilitate the operation test for the semiconductor integrated circuit, therefore, it is necessary to provide the semiconductor integrated circuit with additional input/output terminals dedicated to the test for observing and controlling the internal state thereof and a circuit for aiding the operation test. However, such provision of the test-dedicated input/output terminals leads to various problems in cost and implementability. Thus, there has been proposed a method of controlling the internal state of a semiconductor integrated circuit by separating its internal state into two modes, i.e., a normal operation mode and a test mode.
FIG. 1 is a block diagram showing the structure of a test mode setting circuit in a conventional semiconductor integrated circuit proposed from the aforementioned viewpoint. An example of such a circuit is disclosed in, e.g., Japanese Patent Laying-Open Gazette No. 207648/1983.
Referring to FIG. 1, the conventional test mode setting circuit is formed by an inversion buffer 2 for inverting a signal received from a semiconductor circuit 10 performing normal circuit operation through an output signal line 1 to supply the same to an output pad 3 through a signal line 9, a delay circuit 4 for delaying a signal on the output signal line 9 from the inversion buffer 2 by a predetermined delay time to output the same, an OR gate 5 for receiving an output signal from the delay circuit 4 in one input terminal thereof and receiving a Q output signal from a D-type flip-flop 6 in its other input terminal to obtain the logical sum thereof and output the same and the D-type flip-flop 6 for receiving a signal on the signal line 1 in its input terminal D and receiving an output signal from the OR gate 5 in its clock input terminal CK while receiving a signal supplied through a signal line 8 in its reset input terminal R, to output a signal from an output terminal Q and supply the same to the semiconductor circuit 10 and the other input terminal of the OR gate 5.
The D-type flip-flop 6 outputs the signal supplied at the input terminal D from the output terminal Q on the rising edge of the signal supplied to the clock input terminal CK. The Q output from the D-type flip-flop 6 serves as an operation mode setting signal for the semiconductor circuit 10. Description is now briefly made on the operation of the conventional circuit as shown in FIG. 1.
In a normal operation mode, the D-type flip-flop 6 outputs the signal of logic "0" from the output terminal Q. A signal supplied from the semiconductor circuit 10 on the output signal line 1 is transferred to the output pad 3 through the inversion buffer 2 while being supplied to the delay circuit 4. The delay circuit 4 delays the output signal received from the inversion buffer 2 by a predetermined delay time t.sub.p to supply the same to one input terminal of the OR gate 5. The OR gate 5 obtains the logical sum of the Q output from the D-type flip-flop 6 and the output signal from the delay circuit 4 to supply its output to the clock input terminal CK of the D-type flip-flop 6. The D-type flip-flop 6 outputs the signal supplied in its D input terminal responsive to the rising edge of the signal supplied to the clock input terminal CK from the output terminal Q. The Q output of the D-type flip-flop 6 is reset at logic "0" in the normal operation mode, and hence the OR gate 5 supplies the output (logic "1") of the delay circuit 4 to the clock input terminal CK of the D-type flip-flop 6 at this time.
On the rising edge (transition from "0" to "1") of the output from the delay circuit 4, the signal on the signal line 1 has changed to "0" before the time t.sub.p. Therefore, the D-type flip-flop 6 always outputs the signal of logic "0" from its output terminal Q with no regard to the signal state on the output signal line 1.
In a test mode, a signal of logic "1" appearing on the output signal line 1 is detected by a detecting means (not shown) to forcibly supply the signal of logic "1" to the output pad 3. The Q output of the D-type flip-flop 6 is still "0" at this time, and hence the signal of logic "1" forcibly supplied onto the output pad 3 is supplied to the clock input terminal CK of the D-type flip-flop 6 through the delay circuit 4 and the OR gate 5. Therefore, the signal supplied to the clock input terminal CK of the D-type flip-flop 6 rises from "0" to "1" by the forcibly supplied signal of logic "1", whereby the D-type flip-flop 6 outputs the signal of logic "1" currently on the output signal line 1 from the output terminal Q. The signal of logic "1" from the output terminal Q of the D-type flip-flop 6 is supplied as a test mode command signal to the semiconductor circuit 10 through the signal line 7.
The Q output signal from the D-type flip-flop 6 once converted to "1" is supplied to the clock input terminal CK thereof through the OR gate 5, and hence the D-type flip-flop 6 always outputs the signal of logic "1" from its output terminal Q.
In order to return the circuit from the test mode into the normal operation mode, a system reset is performed to supplying a reset signal to the reset terminal R of the D-type flip-flop 6 through the reset signal line 8, thereby to return the Q output of the D-type flip-flop 6 to "0".
In the test mode setting circuit of the above construction, conversion from the normal operation mode to the test mode must be performed at the time when the output signal on the output signal line 1 is of logic "1", and it is difficult to control such timing of conversion. Further, once the circuit enters the test mode, the entire semiconductor integrated circuit must be reset through a system reset to return the same to the normal operation mode, and it has been impossible to test the circuit operation by temporarily stopping the normal operation of the circuit, i.e., through interruption by the test mode.
TOKE U22 84-059009/10 J5 9016-414-A, "Power-On Reset Circuit", Tokyo Shibaura Denki K. K., 20.07.82-JP-126109 discloses a circuit which operates in a similar manner to a test mode setting circuit according to the present invention. The circuit disclosed in the aforementioned reference is similar to the present invention in that the circuit performs significant operation in accordance with changes in the supply potential level. However, the power-on reset circuit of the above prior art functions only when the supply potential is raised from 0 V to 5 V upon application of power, while the circuit according to the present invention functions when the supply potential is changed from, e.g., 5 V to 8 V and from 8 V to 5 V, i.e., upon bidirectional changes of the supply potential including increase and decrease.